JEDEC剛剛發布了HBM3高頻寬記憶體標準，該標準比現有的HBM2和HBM2e標準大幅提升。
新聞稿：微電子行業標準開發的全球領導者JEDEC固態技術協會今天宣布發布其高頻寬記憶體 (HBM) DRAM標準的下一版本：JESD238 HBM3，可從JEDEC下載網站。HBM3是一種提高數據處理速率的創新方法，用於提高頻寬、降低功耗和單位面積容量對於解決方案的市場成功至關重要的應用，包括顯示處理和高性能計算和伺服器。
新HBM3的主要屬性包括：
- Extending the proven architecture of HBM2 towards even higher bandwidth, doubling the per-pin data rate of HBM2 generation and defining data rates of up to 6.4 Gb/s, equivalent to 819 GB/s per device
- Doubling the number of independent channels from 8 (HBM2) to 16; with two pseudo channels per channel, HBM3 virtually supports 32 channels
- Supporting 4-high, 8-high, and 12-high TSV stacks with provision for a future extension to a 16-high TSV stack
- Enabling a wide range of densities based on 8Gb to 32Gb per memory layer, spanning device densities from 4GB (8Gb 4-high) to 64GB (32Gb 16-high); first-generation HBM3 devices are expected to be based on a 16Gb memory layer
- Addressing the market need for high platform-level RAS (reliability, availability, serviceability), HBM3 introduces strong, symbol-based ECC on-die, as well as real-time error reporting and transparency
- Improved energy efficiency by using low-swing (0.4V) signaling on the host interface and a lower (1.1V) operating voltage
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