找回密碼註冊
作者: sxs112.tw
查看: 7678
回復: 0

文章分享:

+ MORE精選文章:

+ MORE活動推薦:

極致效能優化 三星990 EVO 玩家體驗分享活

[*]進化日常效能 極致效能優化、電源效率提升、廣泛的通用 ...

FSP VITA GM White 玩家開箱體驗分享活動

中秋佳節,全漢加碼活動來囉~ [*]符合最新 Intel ® ATX 3.1電源設 ...

FV150 RGB 玩家開箱體驗分享活動

粉紅控趕快看過來.......廠商加碼活動來囉~ 心動了嗎? 想取得體驗 ...

海韻創新技術分享會 會後分享--得獎公告

頭獎:dwi0342 https://www.xfastest.com/thread-290899-1-1.html ...

打印 上一主題 下一主題

Intel Readies New Memory Controller for Nehalem Chips.

[複製鏈接]| 回復
跳轉到指定樓層
1#
sxs112.tw 發表於 2007-6-12 22:52:07 | 只看該作者 回帖獎勵 |倒序瀏覽 |閱讀模式
Intel’s code-named Nehalem processors have been discussed for nearly five years now, but Intel was tight-lipped enough in order not to disclose details of the new micro-architecture itself as well as implementation peculiarities. Nevertheless, recently Intel started to inform its partners about the future platforms, which means that at least some peculiarities of the new chips have come to light.


It is known that Nehalem as well as Westmere central processing units (CPUs) will use a new platform architecture and while the company does not directly state it, the new platform will hardly use processor system busses, but rather will feature point-to-point serial bus (which is currently referred to as Common Serial Bus or CSI) similar to Hyper-Transport or PCI Express. The new CPUs due in late 2008 will feature so-called dynamically scalable architecture, which means that Intel will be able to tailor its processor designs according to needs of various market segments.

In particular, Intel already announced that, among other things, it would be able to scale and configure caches, interconnect controllers as well as memory controllers. Already now Intel can reduce or increase cache sizes for various processors without many problems, whereas Advanced Micro Devices can enable or disable Hyper-Transport links within its processors depending on their positioning (e.g. AMD Opteron processors for multi-processor servers have three HT links, whereas Athlon 64 for 1P machines have only one HT link). But Intel wants to go even further and scale the number of memory controller channels. According to PC Watch web-site, the top Nehalem processor code-named Bloomfield with four cores will have triple-channel DDR3 memory controller, whereas slightly less advanced may have less channels.

Three memory channels supporting PC3-12800 (DDR3 1600MHz) memory would provide approximately 38.4GB/s memory bandwidth, up significantly from about 21.3GB/s memory bandwidth available today. Given that in 2009 Intel plans to release Nehalem processor with built-in graphics core, triple-channel memory controller may help to keep performance in 3D games on relatively high level.

Intel did not comment on the news-story.


Intel Nehalem to Feature Triple-Channel Memory Controller

xbitlabs
您需要登錄後才可以回帖 登錄 | 註冊 |

本版積分規則

小黑屋|手機版|無圖浏覽|網站地圖|XFastest  

GMT+8, 2024-9-21 11:22 , Processed in 0.751541 second(s), 65 queries .

專業網站主機規劃 威利 100HUB.COM

© 2001-2018

快速回復 返回頂部 返回列表